(1) Field of the Invention
The present invention relates to a phase comparator which is suitable for detecting small phase differences of high-speed pulses used in, for example, tracking correction of optical discs, by suppressing the influence of spike noises occurring in the signals as much as possible.
(2) Description of the Prior Art
Phase comparators have been used in various fields, such as PLL-circuits or various other fields in which a phase comparison result is used for control. The simplest way of configuring a phase comparator is direct use of an exclusive-OR (EX-OR). However, this configuration provides only the phase difference, without any information of phase lead and phase lag. To overcome this, Japanese Patent Application Laid-Open Hei 4 No.234226, proposed a comparator which outputs phase lead and phase lag, independently by detecting leading edges of pulses using flip-flops having an edge-triggered property, as shown in the circuit diagram of this publication.
FIG. 1 shows the circuit diagram of this conventional phase comparator.
FF601 and FF602 are leading-edge triggered D-type flip-flops while FF603 and FF604 are trailing-edge triggered D-type flip-flops. G601 and G602 are AND gates while G603 and G604 are NOR gates.
The D-inputs of all the flip-flops are connected to a power source. The clock inputs to FF601 and FF603 are connected to a lead-phase input terminal Inlead 6 while the clock inputs to FF602 and FF604 are lag-phase input terminal Inlag6. The reset inputs to FF601 and FF602 are connected to the output from G601 while the reset inputs to FF603 and FF604 are connected to the output from G602. The inputs to G601 are the outputs Q601 and Q602 from FF601 and FF602, respectively. The inputs to G602 are the outputs Q603 and Q604 from FF603 and FF604, respectively. The inputs to G603 are the outputs Q601 and Q603 from FF601 and FF603, respectively. The inputs to G604 are connected to the outputs Q602 and Q604 from FF602 and FF604, respectively. The output from G603 is connected to a phase lead output terminal OUTlead6 while the output from G604 is connected to a phase lag output terminal OUTlag6.
In the case where input signal Inlead6 leads input signal Inlag6, upon first transitions (leading edge) of the input signals, the Q-output from FF601 becomes `H` during only the time (phase difference) between the two first transitions (leading edge). Upon second transitions (trailing edge) of the input signals, the Q-output from FF603 becomes `H` during only the time between the two second transitions (trailing edge). Similarly, in the case where input signal Inlead6 lags behind input signal Inlag6, the Q-output from FF602 becomes `H` upon first transitions (leading edge) of the input signals and the Q-output from FF604 becomes `H` upon second transitions (trailing edge) of the input signals. Accordingly, when input signal Inlead6 leads input signal Inlag6, output signal OUTlead6 becomes `L` during only the time of phase difference between two first transitions (leading edge) of the input signals and during only the time of phase difference between two second transitions (trailing edge) of them. When input signal Inlead6 lags behind input signal Inlag6, output signal OUTlag6 becomes `L` during only the time of phase difference between two first transitions (leading edge) of the input signals and during only the time of phase difference between two second transitions (trailing edge) of them.
CMOS circuits need less current consumption, but produce the problem of a large signal delay. So, ECL circuits have been used in the fields where high-speed operations are needed, though the current consumption is high. A leading-edge triggered flip-flop is configured of six gates as shown in FIG. 2. Therefore, the phase comparator shown in FIG. 1 is composed of many gates, that is, twenty-four NAND gates, two AND gates and two NOR gates. If this phase comparator is constructed of ECL circuits, the current consumption for the whole circuit amounts to as much as the current for twenty-eight units of the gate driving current for one gate, so a considerably high current consumption is needed.
When flip-flops having an edge-triggered property are used, if a spike noise arises on the input signal to be edge triggered, it can readily cause malfunction because of the circuit's inherent features. Referring to the timing chart shown in FIG. 3, for example, If a spike noise 1 arises and is input to input terminal Inlag6 during interval t1 to t2, the positive logic, output pulse width PW1 from Q601 is shortened as shown in the chart (the output pulse width PW2 from OUTlead6 is also shortened). Since most phase difference comparators operate by integrating the output pulses, this will not cause fatal influence if a single pulse only is shorted in its pulse width by a spike noise.
However, if, for example, a spike noise 2 arises and input to input terminal Inlag6 during interval t4 to t5, there is a fear that the positive logic, output pulse width PW3 from Q602 might become markedly longer than the original pulse width PW as shown in the chart (the output pulse width PW4 from OUTlag6 also becomes long). In the case where the output is integrated, extremely long pulse widths as in this case produce an erroneous integral.